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Technology >

Advanced Process Technology


NEC Electronics' commitment to R&D excellence is demonstrated evident through numerous groundbreaking advances that have enabled ever smaller devices with ever higher operating speeds and lower power consumption.
Following its successful development of the 65 nm node in 2005, NEC Electronics introduced the first volume 55 nm process to feature a high-k gate insulator, for significantly lower power consumption.
The 55 nm node is based on a miniaturized version of the 65 nm design rule, and is fabricated with state-of-the-art immersion exposure equipment. In addition to lower power consumption, it delivers performance comparable to 45 nm technology.
Meanwhile, work continues on next-generation technology. NEC Electronics expects to begin volume production of 40 nm devices in 2008.


Technology Roadmap
Fig.1 Technology Roadmap

Wide variety of options

To complement its leading-edge CMOS process, NEC Electronics offers numerous on-chip options to meet the requirements of a wide variety of applications.
These options range from embedded DRAM and non-volatile memory to passive elements and bipolar devices. Especially when it comes to high-capacity embedded DRAM, NEC Electronics is the undisputed industry leader.
In 2006, it marked another world first by completing the development of an eDRAM process to complement its leading-edge 55 nm CMOS process. Development of an eDRAM process for the 40 nm node is already underway.


Low power consumption

Through a set of technologies called UltimateLowPower, NEC Electronics has achieved dramatic reductions in both standby and operating power consumption.
For the 55 nm node, an ultra-thin high-k dielectric film cuts power consumption without sacrificing high operating speeds.
These advances make this process the ideal choice for a wide range of applications, from mobile handsets to high-speed network logic.