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The following page content corresponds to the products formerly marketed by NEC Electronics
V850E/MA3 Microcontrollers
Features
- Operating Voltage: 3.0 to 3.6V
- Max. frequency: 80 MHz
- ROM capacities: 256 KB to 512 KB mask ROM and 512 KB flash memory
- RAM capacities: 8/16/32 KB
- Package: 144-pin plastic LQFP and 161-pin plastic FBGA
- Number of instructions: 83
- Minimum instruction execution time: 12.5 ns (at internal 80 MHz operation)
- General-purpose registers: 32 bits x 32
- CPU features:
- Multiplication instruction (16 bits x 16 bits -> 32 bits): 1 to 2 clocks
- Multiplication instruction (32 bits x 32 bits -> 64 bits): 1 to 2 clocks
- Saturated operation instructions (with overflow/underflow detection function)
- 32-bit shift instructions: 1 clock
- Bit manipulation instructions
- Load/store instructions with long/short format
- Signed load instructions - Memory space:
- 256 MB of linear address space (common program/data use)
- Chip select output function: 8 spaces
- Memory block division function: 2, 64 MB/block - External bus interface:
- Separate bus/multiplexed bus output selectable
- 8-/16-bit data bus sizing function
- External bus division function: Divided by 1, 2, 3, 4 (50 MHz max.)
- Wait function
* Programmable wait function
* External wait function
- Idle state function
- Bus hold function
- Address setup wait function
- Endian control function - Memory access controller
- DRAM controller (compatible with SDRAM)
- Page ROM controller - Interrupts and exceptions:
- Non-maskable interrupts: 2 sources (external: 1 source, internal: 1 source)
- Maskable interrupts: 74/75 sources (external: 25 sources, internal: 49/50 sources)
- Software exceptions: 32 sources
- Exception trap: 2 sources
- DMA controller: 4 channels
- Transfer unit: 8 bits/16 bits
- Maximum transfer count: 65,536
- Transfer type: Flyby (1-cycle)/2-cycle
- Transfer mode: Single/Single step/Block
- Transfer target: Memory <-> memory, memory <-> I/O
- Transfer request: External request/On-chip peripheral I/O/Software
- DMA transfer terminate (terminal count) output signal
- Next address setting function - I/O lines: Total: 112
- Timer/counter function:
- Up/down counter/general-purpose timer (TMENC) for 16-bit 2-phase encoder input: 1 channel
- 16-bit interval timer D (TMD): 4 channels
- 16-bit timer/event counter Q (TMQ): 1 channel
- 16-bit timer/event counter P (TMP): 3 channels
- Motor control function (Timers used: TMQ: 1 channel (TMQ0), TMP: 1 channel (TMP2)
- 16-bit accuracy 6-phase PWM function with dead time: 1 channel
- High-impedance output control function
- Timer tuning operation function
- Arbitrary cycle setting function
- Arbitrary dead-time setting function
- Watchdog timer: 1 channel - Serial interfaces:
- Asynchronous serial interface A (UARTA)
- Clocked serial interface B (CSIB)
- I2C bus interface (I2C) (I2C bus versions (Y products) only)
- CSIB/UARTA: 3 channels
- UARTA/I2C: 1 channel - 10-bit resolution A/D converter: 8 channels
- D/A converter: 8-bit resolution: 2 channels
- ROM correction: 4 places can be corrected.
- On-chip debug function
- Clock generator:
- x1.25, 2.5, 5, 10 function via a PLL clock synthesizer (input clock: 4 to 8 MHz)
- External clock input function (input clock: 5 to 25 MHz)
- Power-save function: HALT/IDLE/software STOP mode
- CMOS technology: Fully static circuits
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