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The following page content corresponds to the products formerly marketed by NEC Electronics
V850E/IA3 Microcontrollers
Features
- Operation supply voltage: 4.0 to 5.5 V
- Internal unit: VDD = 2.3 to 2.7 V
- Oscillation block: CVDD = 2.3 to 2.7 V
- External pin: EVDD = 4.0 to 5.5 V (4.5 to 5.5 V when using A/D converters 0 to 2)
- A/D converter block: AVDD = 4.5 to 5.5 V - Max. frequency: 64 MHz
- ROM capacities: 128 KB mask ROM and 256 KB flash memory
- RAM capacities: 6 KB to 12 KB
- Package: 80-pin plastic LQFP package
- Minimum instruction execution time: 15.6 ns (at internal 64 MHz operation)
- General-purpose registers: 32 bits x 32
- CPU features:
- Signed multiplication (16 bits x 16 bits -> 32 bits or 32 bits x 32 bits -> 64 bits):1 to 2 clocks
- Saturated operation instructions (with overflow/underflow detection function)
- 32-bit shift instructions: 1 clock
- Bit manipulation instructions
- Load/store instructions with long/short format
- Signed load instructions - ROM correction: 4 places can be corrected.
- Interrupts/exceptions:
- Non-maskable interrupts: 1 source (external: none, internal: 1)
- Maskable interrupts: 55 sources (external: 7, internal: 48)
- Software exceptions: 32 sources
- Exception traps: 2 sources - DMA controller: 4 channels
- Transfer unit: 8 bits/16 bits
- Maximum transfer count: 65,536
- Transfer type: 2-cycle
- Transfer mode: Single/single step/block
- Transfer target: On-chip peripheral I/O <-> internal RAM, on-chip peripheral I/O <-> on-chip peripheral I/O
- Transfer request: On-chip peripheral I/O/software
- Next address setting function - I/O ports: 50 (Input-only ports: 6, I/O ports: 44)
- Timer/counter function:
- 16-bit up/down counter/timer (TMENC) for 2-phase encoder input: 1 channel
- 16-bit interval timer M (TMM): 1 channel
- 16-bit timer/event counter Q (TMQ): 2 channels
- 16-bit timer/event counter P (TMP): 4 channels
- Motor control function (uses timer TMQ: 1 channel (TMQ0), TMP: 1 channel (TMP0))
- 16-bit accuracy 6-phase PWM function with deadtime: 1 channel
- High-impedance output control function
- Timer tuning operation function
- Arbitrary cycle setting function
- Arbitrary deadtime setting function
- Watchdog timer: 1 channel - Serial interfaces:
- Asynchronous serial interface A (UARTA)
- Clocked serial interface B (CSIB)
- CSIB0: 1 channel
- UARTA0: 1 channel
- CSIB1/UARTA1: 1 channel - 10-bit resolution A/D converters (A/D converters 0 and 1): 2 channels + 4 channels (2 units)
- The two A/D converter 0 channels and three of the four A/D converter 1 channels are provided with an operational amplifier for input level amplification (gain = x2.5, x5) and a comparator for overvoltage detection (input voltage range = 0.1AVDD to 0.5AVDD).
- A/D converter 2, using first-order delta-sigma conversion method: 6 channels - Clock generator:
- 4 to 8 MHz resonator connectable (external clock input prohibited)
- Multiplication function by PLL clock synthesizer (fixed to multiplication by eight, fXX = 32 to 64 MHz)
- PLL operation specifiable by PLLSIN pin
- CPU clock division function (fXX, fXX/2, fXX/4, fXX/8) - Power-save function: HALT/IDLE/STOP mode
- Operation ambient temperature: TA = -40 to +85°C
Development Support
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