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Product Overview

Overview

In recent years, there has been remarkable growth in electronic device products in which semi-custom (ASIC) techniques are used. ASICs are used as key devices in order to bring unique products on time to market.
Of the ASICs, it is Gate Arrays (G/A) that are used widely in communications, manufacturing, office automation, consumer, and amusement products.
An overview of gate array technology is described in this section.

Classification of Gate Arrays at NEC Electronics ASIC

Gate Array Technology Overview

Embedded Array Technology Overview

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Classification of Gate Arrays at NEC Electronics ASIC

Gate Array Technology Overview

Gate Arrays are used to create a specific LSI by executing routing on a master wafer on which gates have been pre-placed in an array formation.

When producing LSIs, the diffusion process that forms elements such as transistors on a silicon wafer takes a long time. With gate arrays, manufacturers can supply wafers called master wafers on which the diffusion process has been completed.
On the master wafer, logic gates (basic cells) are arranged (arrayed) in the shape of a grid. After the circuit to be realized is determined, the basic cells that are not wired to each other and that are electrically independent are combined to realize the digital circuit you desire.

It is possible to develop digital circuits in a short period of time.

It is also possible to produce small volume of digital circuits at low costs.

Channel structure NEC Electronics Gate Array with Channel-less structure The channel Gate Arrays have fixed wiring areas and gate areas. Almost all the gates of these Gate Arrays can be used. However, it is difficult to integrate memories on these Gate Arrays. The channel-less Gate Arrays can be used to integrate a large-scale system on a single chip. They allow users to determine the width of the wiring area and the shape of the gates freely and to integrate memories efficiently.

Gate Arrays Structures

Gate Arrays are composed of the three areas outlined in the following items (1) through (3).

(1) I/O Pad Area

In the I/O pad area, which is an area established for connecting the chip and the package lead frame, connections are made using a procedure known as wire bonding (note that the bonding method may vary depending on the type of package).

(2) I/O Buffer Area

In the I/O buffer area, transistors for connecting the I/O pads and internal cells are placed.

(3) Internal Cell Area

In the internal cell area, transistors are regularly embedded in advance and arrayed on the chip as the smallest unit (called single cell or single gate) that can realize two input NAND gates. Because the circuit size that can be realized is limited by the number of these cells, multiple chip sizes in which the number of cells differ (called masters) are prearranged with NEC Electronics so that users can select an optimal master from among them.

Classification of Gate Arrays

NEC Electronics provides several series of gate arrays according to production processes (chip structures such as gate widths and wiring methods) and the number of embedded gates.

• Product Lineup

Embedded Array Technology Overview

Products known as embedded arrays are also included in the gate array category.
Embedded arrays are high-performance semicustom LSIs that use basic gate array cells in the internal area, but that feature embedded memories and cores of the same type as cell-based ICs. For circuits with high-capacity memory, embedded arrays are the better option in terms of unit price, but development will cost more in order to build the embedded array into the base wafers like cell-based ICs.
Don't hesitate to contact NEC Electronics for a quote to determine whether a gate array or embedded array is the better choice for your design.