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From CPLDs and FPGAs to Gate Arrays

For managers and developers looking for greater cost reduction and improved security, NEC Electronics recommends after prototype design with CPLD/FPGA and mass production with Gate Arrays.

Advantages of Using Gate Arrays	Points to Consider
Notes on Designing Circuits	List of FPGA-Compatible Packages
Sharing Circuit Information

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Advantages of Using Gate Arrays

Points to Consider

Certain considerations must be made before migrating from FPGAs to Gate Arrays. It is necessary to understand the characteristics of both Gate Arrays (custom products) and FPGAs (general-purpose products), and clarify the specifications requirements for the circuit.

Points Gate Arrays FPGA Notes Specifications, i.e. of PLL and memory Are the performance and specifications requirements for the circuit fulfilled? Selectable with the selection wizard provided by the FPGA vendor Pay particular attention to pin functions, timing, operation speed, divider, and multiplier. Specifications of high-speed interfaces, i.e. LVDS Are the performance and specifications requirements for the circuit fulfilled Selectable from multiple specifications provided by the FPGA vendor When using a Gate Arrays, check requirement for compliance with standards such as LVDS. Synchronous design Synchronous design required Can be asynchronous as long as operation is guaranteed - Pin layout design Verification of pin layout required No verification required if functional - Variability design Required Not required - Test design Required Not required Test design requires test pins, test circuits, and test patterns.

Notes on Designing Circuits

For a smooth migration, it is important to bear in mind the differences between Gate Arrays and FPGAs as you design the circuits in RTL.
The circuit design can be targeted at either Gate Arrays or FPGAs, but be sure to note the following.

Point Gate Arrays FPGA IP components such as PLL, memory, and multiplier Standard RTL descriptions (with some special descriptions) RTL descriptions dependent on the FPGA vendor I/O buffer HDL descriptions in the top level No description required Resetting circuits (Initialization of sequential circuits) Requires RTL description for the rest function Not required Clock line RTL description required if using CTS (Clock Tree Sequence) Has embedded clock line Note: Depending on the RTL syntax, circuits generated after logic synthesis may differ for FPGA and Gate Arrays. For details, check with FPGA vendors and logic synthesis tool developers.

List of FPGA-Compatible Packages

Further cost reduction can be achieved by using the same printed board before and after migrating from FPGAs to Gate Arrays. NEC Electronics offers a wide variety of Gate Arrays with dimensions and pin layouts compatible with FPGAs.

Sharing Circuit Information

Sharing Circuit Information with CPLD

CPLD products have relatively small circuit size, with most of the I/O interfaces at the CMOS and TTL levels.
The circuit information can be shared easily with Gate Arrays.

• Sharing circuit information with CPLD

Sharing Circuit Information with FPGA

With the HDL design method now pervasive, circuit information can be shared with FPGA by understanding the characteristics of FPGA and the precautions in Gate Arrays development.

• Sharing circuit information with FPGA