Macro List
NEC Electronics' Gate Arrays and Embedded Arrays are provided with a variety of macros, including I/O macros for high speed interfaces such as SSTL2, SSTL3, and LVDS, as well as mega macros for functions such as serial controllers and parallel interfaces. Embedded Arrays are also available with cell-based IC memory for a higher degree of integration. For information on macros not listed below, contact NEC Electronics.
PLL Macro
Input frequency

|
Parameter
|
CMOS-N5
|
CMOS-9HD
|
EA-9HD
|
CMOS-12M
|
DPLL (F9E4) for skew adjustment
|
-
|
33 to 80
|
33 to 80
|
-
|
DPLL (F9H2) for multiplication
|
-
|
33 to 100(x2) 33 to 80(x1)
|
33 to 100(x2) 33 to 80(x1)
|
-
|
DPLL (F9H3) for multiplication
|
-
|
25 to 100
|
25 to 100
|
-
|
|
Analog PLL
|
-
|
-
|
4 to 160
|
-
|
PLL phase-shift macro
|
-
|
-
|
-
|
25 to 200
|
|
(Unit: MHz)
SSCG Macro Lineup
|
Parameter
|
CMOS-N5
|
CMOS-9HD
|
EA-9HD
|
CMOS-12M
|
PLL SSCG macro for EMI noise reduction
|
-
|
6 to 100
|
6 to 100
|
2 to 200
|
|
(Unit: MHz)
High-speed I/O Lineup
Input/output frequency

|
Parameter
|
CMOS-N5
|
CMOS-9HD
|
EA-9HD
|
CMOS-12M
|
|
VDD=5.0 V
|
VDD=3.3 V
|
VDD=3.3 V
|
VDD=1.5 V
|
|
PCI
|
-
|
33/33
|
33/33
|
66/66
|
|
GTL+
|
-
|
100/100
|
100/100
|
-
|
|
PECL
|
-
|
156/-
|
156/-
|
300/-
|
|
SSTL2
|
-
|
-
|
-
|
300/300
|
|
SSTL3
|
-
|
-
|
-
|
300/300
|
|
LVDS
|
-
|
-
|
-
|
333/333
|
|
(Unit: MHz)
RAM Macro
|
Parameter
|
CMOS-N5
|
CMOS-9HD
|
EA-9HD
|
CMOS-12M
|
Bit-word fixed type RAM
|
High density asynchronous 1-port (4 to 40 bits)
|
16 to 2K
|
16 to 4K
|
16 to 4K
|
-
|
High density asynchronous 2-port (1W+1R) (4 to 40 bits)
|
16 to 512
|
16 to 4K
|
16 to 4K
|
-
|
Compiled type RAM
|
Synchronous 1-port (1 to 128 bits)
|
-
|
-
|
-
|
4 to 1K (1 to 72 bits)
|
Synchronous dual port (1R/W+1R/W) (1 to 128 bits)
|
-
|
-
|
-
|
-
|
Synchronous 2-port (1W+1R) (2 to 128 bits)
|
-
|
4 to 1K
|
-
|
-
|
Synchronous 2-port (1RW+1R) (1 to 72 bits)
|
-
|
-
|
-
|
4 to 1K
|
Asynchronous 1-port (2 to 128 bits)
|
-
|
4 to 1K
|
-
|
-
|
Asynchronous 2-port (1W+1R) (2 to 128 bits)
|
-
|
4 to 1K
|
-
|
-
|
Compiled type RAM (embedded)
|
High-speed synchronous 1-port (1 to 32 bits)
|
-
|
-
|
32 to 2K
|
-
|
High-speed synchronous 2-port (1W+1R) (1 to 32 bits)
|
-
|
-
|
32 to 2K
|
-
|
High-density synchronous 1-port (1 to 32 bits)
|
-
|
-
|
16 to 2K
|
-
|
High-density synchronous 2-port (1W+1R) (1 to 32 bits)
|
-
|
-
|
32 to 1K
|
-
|
Synchronous 1-port (VX type) (1 to 32 bits)
|
-
|
-
|
32 to 8K
|
-
|
Synchronous dual port (1RW+1R) (1 to 32 bits)
|
-
|
-
|
-
|
512 to 16K
|
|
ROM
|
Synchronous (1 to 64 bits)
|
-
|
-
|
64 to 8K
|
-
|
Asynchronous (4 to 32 bits)
|
-
|
128 to 2K
|
128 to 2K
|
-
|
|
(Unit: word count)
Core
|
Parameter
|
CMOS- N5
|
CMOS- 9HD
|
EA- 9HD
|
CMOS- 12M
|
Programmable DMA controller (µPD71037 or equivalent)
|
Ο
|
-
|
-
|
-
|
Serial control unit (µPD71051 or equivalent)
|
Ο
|
Ο
|
Ο
|
-
|
Programmable timer counter (µPD71054 or equivalent)
|
Ο
|
Ο
|
Ο
|
-
|
Parallel interface unit (µPD71055 or equivalent)
|
Ο
|
-
|
-
|
-
|
Interrupt control unit (µPD71059 or equivalent)
|
Ο
|
Ο
|
Ο
|
-
|
UART with FIFO (PC16550D or equivalent)
|
Ο
|
Ο
|
Ο
|
Under development
|
|
PCI macro
|
-
|
-
|
-
|
-
|
|
DDR controller
|
-
|
-
|
-
|
Under development
|
|
Remark
- Ο: Supported, -: Not supported